The present invention relates to a digital data detecting apparatus.
Digital tape recorders which have been developed in recent years record digital audio signals modulated by PCM with k bits (16 bits, for example) in n tracks on a magnetic tape. There has been proposed a circuit, as shown in FIG. 1 of the accompanying drawings, for playing back the magnetic tape on which such digital audio signals are recorded.
As illustrated in FIG. 1, n playback heads 1.sub.1, 1.sub.2, . . . 1.sub.n are arranged transversely across the magnetic tape in alignment with the n tracks, respectively. To the playback heads 1.sub.1 -1.sub.n, there are respectively connected preamplifiers 2.sub.1, 2.sub.2, . . . 2.sub.n, equalizers 3.sub.1, 3.sub.2, . . . 3.sub.n, comparators 4.sub.1, 4.sub.2, . . . 4.sub.n, PLL (phase-locked loop) circuits 5.sub.1, 5.sub.2, . . . 5.sub.n, and data detecting circuits 6.sub.1, 6.sub.2, . . . 6.sub.n.
The circuit arrangement connected to the playback head 1.sub.1 will be described as a typical circuit system. The equalizer 3.sub.1 issues a reproduced signal having an eye pattern as shown in FIG. 2 at A. The actual output waveform of the equalizer 3.sub.1 is an integrated waveform of the positive or negative half wave of the eye pattern which corresponds to the digital data on being recorded. For example, where the data at the time of being recorded comprises the data as shown in FIG. 2 at B, a reproduced waveform after it has been equalized is as illustrated in FIG. 2 at C. The signal from the equalizer 3.sub.1 is applied to the comparator 4.sub.1 in which it is compared with a detection reference level Vs. The comparator 4.sub.1 produces an output as shown in FIG. 2 at D. The comparator output has rising and falling edges displaced due to jitter, and is applied to the PLL circuit 5.sub.1 and the data detecting circuit 6.sub.1. The PLL circuit 5.sub.1 is responsive to the comparator output for generating a clock .phi. in synchronism with the reproduced signal as shown in FIG. 2 at E. The data detecting circuit 6.sub.1 comprises a D flip-flop, for example, for reading the comparator output based on the clock .phi. to gain the original data as shown in FIG. 2 at F. Where the clock has such a phase that a positive-going edge is at 0.degree. and a following negative-going edge at 180.degree., the comparator output is detected at 0.degree.. The falling edge at 180.degree. of the clock .phi. corresponds to the point where the reproduced signal intersects the detection reference level Vs. The detected data is then fed to a digital signal processing circuit 7 for signal processing.
The conventional circuitry shown in FIG. 1 requires n channels of circuit systems each composed of a preamplifier, an equalizer, a comparator, a PLL circuit, and a data detecting circuit, and hence has an increased number of connecting wires, resulting in a complex circuit arrangement. Since the circuitry of FIG. 1 comprises analog circuits, it has been difficult to incorporate integrated circuits in circuit design.